As an example, a conventional signal analyzing apparatus is designed to detect a bit error from an arbitrary section designated in a pattern of a signal outputted from an object under test to measure a bit error rate. The conventional signal analyzing apparatus comprises a pattern position detecting unit, a pattern generating unit, an error counter and a verification unit. The pattern position detecting unit is operable to output a count enable signal when detecting the designated section from the pattern in response to a synchronization signal from the pattern generating unit. The pattern generating unit stores therein patterns of bits to be used for checking the signal outputted from the object under test. The error counter is operable to start and stop counting the number of bit errors in response to a bit error detection signal outputted from the verification unit when receiving the count enable signal from the pattern position detecting unit (refer to for example patent document 1).
Patent document 1: Japanese Patent Laying-Open Publication No. H07-225263